The present disclosure relates to a non-volatile semiconductor memory device including a memory array having a plurality of memory cells, in which the memory array is divided into isolated groups in a bit-line direction, and each memory cell is of, for example, a MONOS type that the cell stores data by locally accumulating charge.
Non-volatile semiconductor memory devices in which a batch of data can be simultaneously electrically erased are characterized in that stored information is not lost even when the device is not powered ON. A variety of arrangements have been proposed for such a kind of non-volatile semiconductor memory devices. In recent years, attention has been attracted by a memory array in which MONOS memory cells which store data by locally accumulating charge are arranged using a virtual ground. This is partly because this technique relatively easily enables each memory cell to store two-bit data.
In this technique, a select transistor is generally provided for each erase unit so as to prevent a voltage from being applied to a bit line for an erase unit which is not to be erased. This means that a large number of select transistors need to be provided so as to increase the erase granularity. Therefore, a layout area for providing the select transistors is increased, disadvantageously leading to an increase in area of the memory array.
In order to solve this problem, a technique of improving the erase granularity without providing a select transistor has been proposed in which a memory array is divided into a plurality of bit line groups, where an isolation region is provided between each bit line group (Patent Document 1).
FIG. 4 is a diagram showing an example memory array arrangement of a conventional non-volatile semiconductor memory device.
Read operation in the arrangement of FIG. 4 will be described. Here, it is assumed that a memory cell 401 is connected to WL0 of word lines 402 and BL1 and BL2 of bit lines 403, and data stored on the BL2 side thereof is read out.
Initially, a word line selecting circuit 412 applies a read voltage to WL0 while applying 0 V to the other word lines.
In addition, a read drain voltage is applied to BL1 while a read source voltage is applied to BL2, where the read drain voltage is higher than the read source voltage. As a result, data can be read out, depending on the amount of a current passing through the memory cell 401 (the current amount depends on a charge accumulated state on the BL2 side). In this case, a voltage control circuit a 410 generates the read drain voltage, and a voltage control circuit b 411 generates the read source voltage. Also, BSL0 is selected from bit switching transistors 409, MSL0 and MSL1 are selected from MBL selecting transistors 408, and SL0 and SL1 are selected from select transistors 407.
Conversely, when data stored on the BL1 side is read out, the source voltage is applied to BL1 while the drain voltage is applied to BL2. This is achieved by selecting BSL1 from the bit select transistors 409. The MBL selecting transistors 408 and the select transistors 407, and the word lines 402 are selected in manners similar to those when data on the BL2 side is read out.
Next, write operation in the arrangement of FIG. 4 will be described. Here, it is assumed that, as is similar to the read operation, attention is paid to the memory cell 401 which is connected to WL0 of the word lines 402 and BL1 and BL2 of the bit lines 403, and data is to be stored on the BL2 side thereof by locally accumulating charge.
Initially, the word line selecting circuit 412 applies a write voltage to WL0 while applying 0 V to the other word lines 402.
In addition, 0 V is applied to BL1 while a high voltage is applied to BL2. As a result, a current passes through the memory cell 401, so that charge is accumulated on the BL2 side by channel hot electrons, whereby data can be written. In this case, the voltage control circuit a 410 generates 0 V while the voltage control circuit b 411 generates a voltage Vdp+ΔVdp. The term ΔVdp represents a voltage including a voltage drop across a bit switching transistor 409, an MBL selecting transistor 408 and a select transistor 407 of a current passing through a memory cell during write operation, and a voltage drop due to a resistance of a main bit line 404. In addition, BSL0 is selected from the bit switching transistors 409, MSL0 and MSL1 are selected from the MBL selecting transistors 408, and SL0 and SL2 are selected from the select transistors 407.
After application of the write voltage, program verification is executed to determine whether or not a predetermined Vt has been reached. When the predetermined Vt has not been reached, a voltage is applied again. When the predetermined Vt has been reached, the voltage application is stopped. Thus, the write operation is completed.
Conversely, when data is written to the BL1 side, Vdp is applied to BL1 while 0 V is applied to BL2. This is achieved by selecting BSL1 from the bit select transistors 409. The MBL selecting transistors 408 and the select transistors 407, and the word lines 402 are selected in manners similar to those when data is written to the BL2 side.
Next, erase operation will be described. In a non-volatile semiconductor memory device in which a batch of data can be simultaneously electrically erased, a predetermined number of bits (1 Mb, etc.) are simultaneously erased as an erase unit. A case where data is erased from memory cells 401 in a usable region 405 provided between two isolation regions in the arrangement of FIG. 4, will be described.
Initially, before start of erasure, write operation is executed with respect to data in the erased state within an erase unit to provide a uniform Vt within the erase unit (preprogramming step). Thereafter, an erase voltage generated by the voltage control circuit b 411 is applied to a bit line 403 to inject hot holes occurring between the bit line 403 and a substrate into an area in which electric charge is locally accumulated, thereby neutralizing the electric charge locally accumulated on the bit line side of each memory cell 401. As a result, data is erased.
In this case, an erase voltage Vde is normally applied to either of two bit lines 403 connected to memory cells 401, but not to both of them. The other bit line is not electrically connected (HiZ state).
As the number of bit lines to which a voltage is simultaneously applied increases, a time required for erasure advantageously decreases. However, this number is limited by a current caused by a current passing through a memory cell (hereinafter referred to as “Ie”) during erasure and a current capability (hereinafter referred to as “Ipp”) of the voltage control circuit b 411 which is used to apply a voltage to a bit line. In order to increase the number of bit lines to which a voltage is simultaneously applied, the Ipp of the voltage control circuit b 411 needs to be increased, which leads to an increase in chip area.
Therefore, in order to achieve a chip having a small area, it is necessary to reduce the number of bit lines to which a voltage is simultaneously applied, i.e., to divide bit lines into a plurality of groups in an erase unit and apply an erase voltage to the groups separately. Specifically, the following expression needs to be satisfied:Ipp>Ie×i where i represents the number of bit lines to which a voltage is simultaneously applied.
For example, erase operation in a case where the number i of bit lines to which a voltage is simultaneously applied is two, will be described with reference to FIGS. 5A and 5B. FIG. 5A is a diagram showing timings of application of a voltage to word lines 402 and bit lines 403 when the erase operation is executed with respect to the usable region 405. FIG. 5B is a diagram showing bit lines to which an erase voltage is applied at each timing.
Initially, the word line selecting circuit 412 applies an erase voltage Vwle to the word lines 402 (WL0 to WLm).
Thereafter, the voltage control circuit b 411 generates a voltage Vde+ΔVde. The term ΔVde represents a voltage including a voltage drop across a bit switching transistor 409, an MBL selecting transistor 408 and a select transistor 407 of a current passing through memory cells in the erase operation, and a voltage drop due to a resistance of a main bit line 404. In addition, BSL0 is selected from the bit switching transistors 409, MSL1 is selected from the MBL selecting transistors 408, and SL0 and SL1 are selected from the select transistors 407. Therefore, the erase voltage Vde is applied to BL1 and BL3 of the bit lines 403. As a result, electric charge locally accumulated on the BL1 and BL3 sides of the memory cells 401 connected to BL1 and BL3 is neutralized (step E_0).
Next, the selected MBL selecting transistor 408 is changed from MSL1 to MSL3, so that the erase voltage Vde is applied to BL5 and BL7 of the bit lines 403. As a result, electric charge locally accumulated on the BL5 and BL7 sides of the memory cells 401 connected to BL5 and BL7 is neutralized (step E_1).
Thereafter, a similar control is repeatedly executed while changing the selected MBL selecting transistor 408, until MSLn−1 is selected (step E_j−1).
Thereafter, the bit switching transistor is changed from BSL0 to BSL1, MSL0 is selected from the MBL selecting transistors 408, and SL0 and SL1 are selected from the select transistors 407. As a result, BL0 and BL2 are selected from the bit lines 403 (step E_j).
Thereafter, a similar control is repeatedly executed while changing the selected MBL selecting transistor 408, until MSLn is selected (step E_n).
After a series of erase voltage applications, erasure verification is executed to determine whether or not the predetermined Vt has been reached. When the predetermined Vt has not been reached, a series of erase voltage applications are executed again. When the predetermined Vt has been reached, the voltage application is stopped. Thus, the erase operation is completed.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-039233